1. Field of the Invention
The present invention relates to a semiconductor memory device capable of performing a low-frequency test operation and a method for testing the same, and more particularly, to a semiconductor memory device capable of performing a low-frequency test operation even when a high-frequency external clock signal is input and a method for testing the same.
2. Description of the Related Art
With the popularity of consumer electronics, the operating speed of semiconductor memory devices continues to increase. A synchronous semiconductor memory device operates in synchronization with an external clock signal input from an external device. As the frequency of the external clock signal increases, the operating speed of the synchronous semiconductor memory device also increases.
A test apparatus provides a plurality of external control signals and an external clock signal to a synchronous semiconductor memory device and inspects test data writing and reading operations of the synchronous semiconductor memory device to determine whether the synchronous semiconductor memory device is operating properly.
FIG. 1 illustrates a test operation of a semiconductor memory device 120. The semiconductor memory device 120 receives a plurality of external control signals C1, C2, C3, . . . and an external clock signal EXCLK from a test apparatus 110 and performs an operation of writing test data D from DQ or an operation of reading test data Q from DQ based on an internal clock signal INCLK generated from the external clock signal EXCLK.
When the semiconductor memory device 120 buffers the external clock signal EXCLK to generate the internal clock signal INCLK, the internal clock signal INCLK has a high frequency when the external clock signal EXCLK has a high frequency and the internal clock signal INCLK has a low frequency when the external clock signal EXCLK has a low frequency. The semiconductor memory device 120 can, in some cases, double a low-frequency external clock signal EXCLK to generate a high-frequency internal clock signal INCLK. An inexpensive test apparatus can provide the low-frequency external clock signal EXCLK while an expensive test apparatus can provide the high-frequency external clock signal EXCLK.
As the operating speed of the semiconductor memory device 120 increases, the operation speed of the test apparatus 110 is more significant in testing of the performance of a high-frequency operation of the semiconductor memory device 120. There is no problem if defects of the semiconductor memory device 120 can be all detected by the test of the high-frequency operation of the semiconductor memory device 120. However, some defects of the semiconductor memory device 120 are manifested only in a low-frequency operation environment; thus, a performance test of the high-frequency operation of the device cannot detect this particular defect. If the high-frequency operation of the semiconductor memory device 120 is tested using a first test apparatus providing a high-frequency external clock signal and the low-frequency operation of the semiconductor memory device 120 is tested using a second test apparatus providing a low-frequency external clock signal, the cost of performing the test will be considerably increased.